This article explains the interface and protocol used by IDE disc drives, which I have studied in order to implement it myself. I wrote this article in order to both reinforce my knowledge and provide a educational resource for others interested in creating a DIY implementation. The extent of detail is enough to send ATAPI commands to an optical disc drive for track control and information. I may in the future decide to develop this further, but this is the current intended scope of this article. This is a summary of information I pulled together from various sites, resources and specifications.
Disambiguation: There are a few names used interchangeably for the 40-pin interface. The big three are ATA (AT attachment, the "official" name), IDE (integrated drive electronics) and PATA (parallel ATA, retroactively termed after the introduction of SATA). When (P)ATA or IDE are mentioned in this article, they can be assumed to mean the 40-pin bus that was historically used to connect hard disks and optical drives to a motherboard or controller.
Below is the pinout of the 40-pin connector used by IDE devices:
| alternate name | signal | Pin nr. | Pin nr. | signal | alternate name |
|---|---|---|---|---|---|
| RESET_n | 1 | 2 | GND | ||
| D7 | 3 | 4 | D8 | ||
| D6 | 5 | 6 | D9 | ||
| D5 | 7 | 8 | D10 | ||
| D4 | 9 | 10 | D11 | ||
| D3 | 11 | 12 | D12 | ||
| D2 | 13 | 14 | D13 | ||
| D1 | 15 | 16 | D14 | ||
| D0 | 17 | 18 | D15 | ||
| GND | 19 | 20 | Key | ||
| DMARQ | 21 | 22 | GND | ||
| DIOW_n | 23 | 24 | GND | ||
| DIOR_n | 25 | 26 | GND | ||
| IORDY | 27 | 28 | CSEL | ||
| DMACK_n | 29 | 30 | GND | ||
| INTRQ | 31 | 32 | IOCS16_n | ||
| A1 | 33 | 34 | PDIAG_n | ||
| A0 | 35 | 36 | A2 | ||
| CS0_n | CS1FX_n | 37 | 38 | CS3FX_n | CS1_n |
| DASP_n | 39 | 40 | GND |
Signals with a _n suffix are active low
| Signal | Description | Direction |
|---|---|---|
| RESET_n | When asserted, resets all drives on an IDE chain | Host -> Drive |
| A0 - A2 | 3 bit address bus used to select a register in a drive's task file | Host -> Drive |
| D0 - D15 | Bidirectional 16 bit data bus between host and drives | Bidirectional |
| CS0_n | Register select. Selects the command block of the task file. | Host -> Drive |
| CS1_n | Register select. Selects the control block of the task file. | Host -> Drive |
| DIOW_n | IO write pulse. Assert when writing to task file. | Host -> Drive |
| DIOR_n | IO read pulse. Assert when reading from task file. | Host -> Drive |
| IORDY | Driven low by a drive to signal to the host to slow down read/write cycles by inserting wait states. | Drive -> Host |
| DMARQ_n | DMA request. Asserted by a drive to request a DMA transfer to or from the host | Drive -> Host |
| DMACK_n | DMA acknowledge. Asserted by the host to initiate a DMA transfer in response to DMARQ_n | Host -> Drive |
| INTRQ | Interrupt request. Signals a completed command or transfer to the host. | Drive -> Host |
| DASP_n | Drive active/slave present. Used by drive 1 (slave) to indicate presence during boot sequence. After that, it may be used by either drive to indicate activity. Open-collector output. | |
| CSEL | When a drive is jumpered for cable select, this pin determines its address. If CSEL is grounded, the drive's address is 0. If CSEL is open, the drive's address is 1. | |
| PDIAG_n | Asserted by drive 1 to indicate to drive 0 that it has passed diagnostics. | Drive 1 -> Drive 0 |
| IOCS16_n | Obsolete. Unused by optical drives. If this signal is asserted and PIO mode is used for data transfer, data transfers will be 16 bit. If negative, PIO data transfers will be 8 bit | Drive -> Host |
ATA devices contain two blocks of 8 registers each which are collectively refered to as the "task file". The task file is accessible over the IDE bus. A register is selected using the A0 - A2 pins, and a block is selected using either one (but not both) of CS0_n or CS1_n. Register functions are dependent on whether the address is being written or read. Vacant cells in the address and CS columns have a value of zero. The zeroes were omitted for readability.
| CS1_n | CS0_n | A2 | A1 | A0 | Register purpose | |
|---|---|---|---|---|---|---|
| Read | Write | |||||
| Command block | ||||||
| 1 | Data | |||||
| 1 | 1 | Error register | Features register | |||
| 1 | 1 | Sector Count | ||||
| 1 | 1 | 1 | Sector Number | |||
| 1 | 1 | Cylinder Low | ||||
| 1 | 1 | 1 | Cylinder High | |||
| 1 | 1 | 1 | Drive/Head | |||
| 1 | 1 | 1 | 1 | Status | Command | |
| Control block | ||||||
| 1 | ||||||
| 1 | 1 | |||||
| 1 | 1 | |||||
| 1 | 1 | 1 | ||||
| 1 | 1 | |||||
| 1 | 1 | 1 | ||||
| 1 | 1 | 1 | Alternate status | Device Control | ||
| 1 | 1 | 1 | 1 | Drive address | ||
The register names in Table 3. are true for ATA hard disks. These registers are used by a host (e.g. IDE controller card) to perform read and write operations. This is useful context to know but the workings are slightly different for CD and DVD drives.
ATAPI (ATA packet interface) is an extension of ATA used in optical drives that allows SCSI commands to be given to ATA devices by transmitting them in packets. Like ATA, ATAPI devices also have a task file addressable over the 40-pin physical interface, but the register functions and purposes are different.
| CS1_n | CS0_n | A2 | A1 | A0 | Register purpose | |
|---|---|---|---|---|---|---|
| Read | Write | |||||
| Command block | ||||||
| 1 | Data | |||||
| 1 | 1 | ATAPI Error register | ATAPI Features register | |||
| 1 | 1 | ATAPI interrupt reason register | ||||
| 1 | 1 | 1 | ||||
| 1 | 1 | ATAPI byte count register (bits 0-7) | ||||
| 1 | 1 | 1 | ATAPI byte count register (bits 8-15) | |||
| 1 | 1 | 1 | Drive select | |||
| 1 | 1 | 1 | 1 | ATAPI Status | ATAPI Command | |
| Control block | ||||||
| 1 | ||||||
| 1 | 1 | |||||
| 1 | 1 | |||||
| 1 | 1 | 1 | ||||
| 1 | 1 | |||||
| 1 | 1 | 1 | ||||
| 1 | 1 | 1 | Alternate ATAPI status | Device Control | ||
| 1 | 1 | 1 | 1 | |||
The control block contains various registers that are reserved for future use or are not used by ATAPI. Only one register in this block is used, at address 0b110. Writing to this register allows for "Device Control" as per its name, and according to SFF-8020i (the ATAPI specification), can be used to initiate a soft reset, or enable/disable the generation of interrupts on the INTRQ pin. Reading this register gives "Alternate ATAPI Status", which has the same value as "ATAPI status" in the command block, but reading the alternate status does not clear or acknowledge an interrupt. It may be possible to reduce a DIY ATAPI implementation by one pin & signal by choosing to not need to address the control block, if interrupts and soft resets will not be used.
Only the lower eight bits of the data bus are used when issuing commands, and the full width of the bus is used only for data transfers (e.g. identify drive, read table of contents & time). If a project needs to write commands to an optical drive, but not read anything from it, it is possible to reduce the DIY ATAPI implementation by eight pins and signals as the upper byte of the data bus will be unused, at a cost of not being able to detect a drive (the full width is needed for this). If this reduction is applied, it will be impossible to implement an ATAPI device detection check.
Page created: 22MAR2026
Last modified: 25MAR2026